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ModelSIM – Download Link – Workshop on Digital System Lab using Verilog

Pantech E Learning is organizing a workshop on Digital Systems Lab using Verilog on Feb 01 & 02, 2021 , targeting Graduate engineering staffs & students to equip themselves in Digital Systems Lab & Verilog .

Key Speaker : Dr. R. Sakthivel Ramachandran M.E, Ph.D.,Sr. IEEE ACM’s Distinguished Speaker,VIT Vellore.

Workshop Content:

  • Procedure for Installation and Simulation of Modelsim.
  • Basic Gates Using Dataflow, Structural, Behavioral Modeling
  • Adder -Subtractor using structural/dataflow Modeling
  • Decoder and Encoder using case, casex and casez statements.
  • Code Convertor & parity generators using reduction operators
  • Multiplexer and De-multiplexer using nested if-else construct
  • Flip-Flop, SISO,PIPO,SIPO,PISO
  • Counter Design
  • FSM Design-The State table and State Diagram
  • Mealy or Moore machines

 

Workshop Benefits

  • Get strong accumulated knowledge of Digital Lab Systems & Verilog.
  • Understand the Digital Labs Curriculum and explore its potential.
  • Get hand-on experience and work towards the syllabus .

 

Software Download Links:

Software ModelSIM ( Student Version ) can be downloaded from the link below

ModelSIM

Model SIM Download Link

 

Pantech E Learning Co-ordinators :  8925533488 / 89

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