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Pantech E Learning is organizing a workshop on Digital Systems Lab using Verilog on Feb 01 & 02, 2021 , targeting Graduate engineering staffs & students to equip themselves in Digital Systems Lab & Verilog .
Key Speaker : Dr. R. Sakthivel Ramachandran M.E, Ph.D.,Sr. IEEE ACM’s Distinguished Speaker,VIT Vellore.
Software Download Links:
Software ModelSIM ( Student Version ) can be downloaded from the link below
Pantech E Learning Co-ordinators : 8925533488 / 89