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Workshop on High Speed CMOS Logic Design

Workshop on High Speed CMOS Logic Design

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  • ₹350.00 VLSI Workshop 157 remaining
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Workshop on High Speed CMOS Logic Design

2021-01-21 17:00 to 2021-01-23 19:30
January 21, 2021

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Pantech eLearning

8925533488

training@pantechelearning.com

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Workshop on High Speed CMOS Logic Design

2021-01-21 17:00 to 2021-01-23 19:30
January 21, 2021

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Session 1:
– MOS Capacitors
– Method of Logical Effort
– Transistor Sizing for Minimum Delay
– Path Sizing for Minimum Delay
– Stick Diagram
– Area Estimation
Session 2:
– Schematic Based Design Entry
– Pre-Layout Simulation
– Measurement of FoMs
– Corner Analysis
– Monte Carlo Simulation
Session 3:
– Layout of CMOS Circuit
– DRC Check
– LVS Check
– Post Layout Simulation
– Measurement of FoMs
– Comparison of Pre-Layout and Post Layout Simulation

Tools:

Open source Tools (LTSpice and ELECTRIC)

 

Target Audience:

The workshop can be attended by Research scholars, Faculty members, U.G/ P.G students from ECE/EEE/TCE, and Industry Professionals.

 

Resource Person:

Dr. Naushad Alam,
PhD from IIT Roorkee,
Department of Electronics Engineering,
ZHCET, AMU Aligarh University.

 

Take Aways:

  • A Complete Practical Knowledge on CMOS Design
  • Workshop Certification
  • Materials
  • Recorded Videos
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