Design of a Dual Port RAM using Verilog

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With the advent of portable devices, the demand for static random-access memory (SRAM) is increasing with large use of SRAM in System on Chip and high-performance VLSI circuits. SRAM optimization has become a focal point for research work, as 60% to 70% area of the chip is consumed by the memories. The performance parameters optimization can lead to the overall optimization of the performance of the chip. In this paper design and analysis of the 8T SRAM cell at different technologies using PTM (Predictive Technology Model) model has done with the aim of reducing power dissipation while maintaining stability.

Then the performance of SRAM cell is compared on the basis of power dissipation i.e. dynamic power dissipation and static power dissipation, delay, Power Delay Product (PDP) and Static Noise Margin (SNM).SRAM cell read stability and write-stability are major concerns in nanometer CMOS technologies, due to the progressive increase in intra-die variability and Vdd scaling. Cell stability is also examined by the calculation of SNM with the help of the butterfly curve method at different CMOS technologies. Effect of variation of channel length on static power consumption, dynamic power consumption, delay, PDP and SNM is also measured. SNM variation is also observed with the variation of the supply voltage.

Keywords: Power dissipation (Static and Dynamic Power Dissipation), Delay, Power Delay Product, Static Noise Margin, Stability


Static Random Access (SRAM) constitutes a large percentage of area in the VLSI designs due to the high number of transistors for a single SRAM cell. Thus, the SRAM cell generally employsa minimum size transistor to have a high packing density [1].The size of the SRAM cell is being reduced using scaling over the past three decades [2].SRAM takes two design aspects: the power dissipation and propagation delay in reading and writing the value into the SRAM cell. The power dissipated during read and write operation is dynamic power dissipation. It helps to determine the battery life of portable devices. The speed of SRAM is determined by the delay in reading and writing [3]. In nanometre design, many design challenges occur due to device scaling [4].

The main concern for SRAM cell design is stability. Stability of memory is affected by the aspect ratio of MOSFET and operating conditions. The aim of stability in memory is to operate it correctly. The measure of stability in the SRAM cell is Static Noise Margin (SNM).The voltage transfer characteristics of the SRAM cell are used to obtain the SNM [5].SNM is the lowest voltage noise that can flip the state of SRAM [6]. While reading the stored data from SRAM, the stored value should not alter and SRAM should allow new data to be written into it during write phase [7]. Dynamic power dissipation and static power dissipation comprises the total power dissipation of SRAM.

The dynamic power is consumed during the normal operation of the SRAM i.e. read and write whereas the standby power is consumed during the standby state [8]. The main objective of this paper is to design and analysis of 8T SRAM cell at different CMOS technologies with stability analysis. For this analysis, PTM model cards (Predictive Technology Model) are selected to explore the performance characterization in different modes of the cell. It provides accurate and compatible model files with a wide range of process variations [9, 10].The designs and simulations are carried out using Cadence Virtuoso Analog Design Environment. CMOS devices have been scaled down in order to achieve higher speed, performance and lower power consumption. SRAM means Static Random Access Memory.

The SRAM cell that we considered in this paper was 6T SRAM cell which consists of two crossly coupled inverters and access transistors to read and write the data. In case of the SRAM cell the memory built is being stored around the two cross coupled inverters. If we consider that, the input to the first inverter is logic 1 then the output of this inverter will be logic 0. So, after one cycle the output of second inverter will be logic 1. From this we can say that as long as the power is supplied to the SRAM cell logic 1 will be circulated in the inverters. Hence there is no need for periodic refreshing of the circuit. Where as in DRAM the circuit need to be refreshed periodically . SRAM technology is most preferable because of its speed and robustness [3]. Therefore, SRAM is much faster when compared with the DRAM.


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