Design and Analysis of Area and Power Efficient Approximate Booth Multipliers

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Design and Analysis of Area and Power Efficient Approximate Booth Multipliers

Approximate computing is an emerging technique in which power-efficient circuits are designed with reduced complexity in exchange for some loss inaccuracy. Such circuits are suitable for applications in which high accuracy is not a strict requirement. Radix-4 Modified Booth encoding is a popular multiplication algorithm that reduces the size of the partial product array by half. In this paper, three Approximate Booth Multiplier Models (ABM-M1, ABM-M2, and ABM-M3) are proposed in which approximate computing is applied to the radix-4 modifed Booth algorithm. Each of the three designs features a unique approximation technique that involves both reducing the logic complexity of the Booth partial product generator and modifying the method of partial product accumulation. The proposed approximate multipliers are demonstrated to have better performance than existing approximate Booth multipliers in terms of accuracy and power. Compared to the exact Booth multiplier, ABM-M1 achieves up to a 23 percent reduction in area and 15 percent reduction in power with a Mean Relative Error Distance value of 7:9*10^-4 ABM-M2 has an area and power savings of up to 51 and 46 percent respectively with an MRED of 2:7*10^2. ABM-M3 has area savings of up to 56 percent and power savings of up to 46 percent with an MRED of 3:4*10^3. The proposed designs are compared with the state-of-the-art existing multipliers and are found to outperform them in terms of area and power savings while maintaining high accuracy. The performance of the proposed designs is demonstrated using image transformation, matrix multiplication, and Finite Impulse Response (FIR) filtering applications.

Digital systems are highly complex at their most detailed level. They may consist of millions of elements i.e., transistors or logic gates. For many decades, logic schematics served as the tongue. Franca of logic design, but not anymore. Today, hardware complexity has grown to such a degree that a schematic with logic gates is almost useless as it shows only a web of connectivity and not the functionality of the design. Since the 1970s, computer engineers, electrical engineers, and electronics engineers have moved toward Hardware description language (HDLs).Design and Analysis of Area and Power Efficient Approximate Booth Multipliers


  • The design process is the final stage of implementation.
  • coding and RTL can be Implemented using Integrated circuits.



The typical design flow for designing VLSI circuits is shown in the tool flow diagram. This design flow is typically used by designers who use HDLs. In any design, specification is first. The specification describes the functionality, interface, and overall architecture of the digital circuit to be designed. At this point, architects need not think about how they will implement their circuits. A behavioral description is then created to analyze the design in terms of functionality, performance, and other high-level issues. The behavioral description is manually converted to an RTL (Register Transfer Level) description in an HDL. The designer has to describe the data flow that will implement the desired digital circuit. From this point onward the design process is done with the assistance of CAD tools. Literature survey

Approximate computing is an attractive design methodology to achieve low power, high performance (low delay), and reduced circuit complexity by relaxing the requirement of accuracy. In this paper, approximate Booth multipliers are designed based on approximate radix-4 modified Booth encoding (MBE) algorithms and a regular partial product array that employs an approximate Wallace tree. Two approximate Booth encoders are proposed and analyzed for error-tolerant computing. The results show that the proposed 16-bit approximate radix-4 Booth multipliers with approximate factors of 12 and 14 are more accurate than existing approximate Booth multipliers with moderate power consumption. The proposed R4ABM2 multiplier with an approximation factor of 14 is the most efficient design when considering both the power-delay product and the error metric NMED. Case studies for image processing show the validity of the proposed approximate radix-4 Booth multipliers.


    1. J. Han and M. Orshansky. ?Approximate Computing: An Emerging Paradigm for Energy-Efficient Design.” In approaches of the eighteenth IEEE European Test Symposium, Avignon, France, May 2013, pp.1-6.
    2. J. Liang, J. Han and F. Lombardi.” New measurements for the unwavering best of envisioned and probabilistic adders.”IEEE Trans. PCs. Vol. Sixty-two, no.9, pp.1760-1771, Sept. 2013.
    3. Momeni, J. Han, P. Montuschi and F. Lombardi.”Structure and Analysis of Approximate Compressors for Multiplication.” IEEE Trans. PCs, vol.64, no.4, pp. 984-994, Apr. 2015.

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