Chromosome Type Classification using Deep Learning | OpenCV


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For SRAM power, stability, delay and area are the major concerns. And they are trade-offs to each other. But all are important and should be in acceptable range. In this paper we mainly concentrated on power and stability and we designed an optimized proposed 9T-SRAM for low power consumption by placing an NMOS transistor between supply voltage VDD and the latches formed by cross coupled inverters. This NMOS transistor is in diode connected mode and it scales down the VDD. So total power is reduced by 98%. Because power is directly proportional to square of VDD. But this effect the stability, as stability decreases when supply voltage decreases. In order to increase stability an extra PMOS transistor is placed in between access transistor and pull down transistor. This PMOS transistor separate?s the storage node and writing node of data. It also scales the bit line voltage and prevent the flipping the contents of cell at low voltages. So stability parameters like SINM, SVNM, WTI and WTV also increased by 93%, 45%, 86% and 56% respectively. In this proposed cell static power is also reduced by 55% due to stacking effect. This all values are when compared with Sub-threshold 10T SRAM cell. This proposed circuit is also tested by giving 0.3 V power supply.

Cadence Virtuoso tools are used for simulation with gpdk-90nm CMOS process technology.


Existing System

6T SRAM cell:

N1 and N2 NMOS transistors act as driver transistors. P1 and P2 PMOS transistors which act as load transistors. These four transistors combine and form cross coupled inverters to store and force values continuously to each other. N3 and N4 act as pass transistors and called as access transistor which helps to write data from bit lines to node Q and QB.

Modes of Working

Write mode:

To write the data in to the cell we first enable write line (WL).

BL =1 and BLB= 0

BL =0 and BLB= 1 After writing the data WL line is disabled. To write ?0? we pass ?0? to bit line (BL) and ?1? to bit line bar (BLB).

Hold mode:

In hold mode WL remains disabled and disconnects the cell from bit lines.

Cross coupled inverters force values continuously to each other and stores the written data at Q and QB nodes.

Read mode:

If stored data is ?1? then N1 is OFF and N2 is ON. Pre-charged BL line has no path to ground, so it remains as ?1?at node Q and precharged BLB is discharged through N4 and N2 to ground, so it reads ?0? from node QB.

If stored data is ?0? then N1 is ON and N2 is OFF. BL discharged through N3 and N1 to ground, so it reads ?0?from node Q.

Proposed System


The stability decreased due to scaling of VDD is compensated in 6T SRAM

This structure increases the read stability by the extra PMOS transistors P3 and P4 which are always ON are added in between driver and access transistors.


[1] Analysis of Low Power SRAM Memory Cell using Tanner tool by SimranKaur, Ashwani Kumar.

[2] Leakage Characterization of 10T SRAM Cell byA. Islam, Member, IEEE, and M. Hasan, Member, IEEE

[3] Design and Statistical analysis of Low-Power Proposed SRAM cell Structure by Govind Prasad.

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