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A low-power high speed 4-2 compressor circuit is proposed for fast digital arithmetic integrated circuits. The 4-2 compressor has been widely employed for multiplier realizations. Based on a new exclusive OR (XOR) and exclusive NOR (XNOR) module, a 4-2 compressor circuit has been designed.
Proposed circuit shows power consumption variation in the range of 718.72 pW to 3357.40 pW. Maximum output delay of the circuit presents variation in the range of 43.83 ps to 27.74 ps. Further, power-delay product (PDP) of circuit is varying from 315.01?10-22(J) to 931.34?10-22(J) with change in supply voltage from 1.8V to 3.3V. Power consumption, delay and PDP of proposed 4-2 compressor circuit have been compared with earlier reported circuits and proposed circuit is proven to have the minimum power consumption and the lowest delay. Simulations have been performed by using SPICE based on TSMC 0.18?m CMOS technology.
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