A high speed design of 16 bit Vedic Multiplier

SKU: PAN_VLSI_015 Category:

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ABSTRACT

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Speed and occupational area are key in RISCs (Reduced Instruction Set Computers), DSPs (Digital Signal Processors). Knowing that most of the operations involved in processing signal are multiplications since fundamental process in communication ?modulation? is multiplication. This paper introducing architecture to perform high speed multiplication using one of the methods Urdhva-tiryakbhyam from Vedic maths technique. Here in this a 4:2 compressor, 7:2 compressors and 15:2 compressors technique are used to increase speed. Upon comparison, the compressor based multiplier has improvement in speed and area with some stranded methods like array and booth

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