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Workshop on HDL based VLSI System Design using ModelSim

Workshop on HDL based VLSI System Design using ModelSim

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Workshop on HDL based VLSI System Design using ModelSim

2021-06-17 17:30 to 2021-06-19 19:00
June 17, 2021

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Pantech eLearning

8925533488

training@pantechelearning.com

https://www.pantechelearning.com/

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Workshop on HDL based VLSI System Design using ModelSim

2021-06-17 17:30 to 2021-06-19 19:00
June 17, 2021

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This workshop provides participants an insight into the processes involved in taking a Analog and Digital System Design. Whilst emphasizing the online tools’ availability and their installation procedures, this workshop also focuses on simulating several other experiments below, to develop the basic understanding of the VLSI System design using HDL.

 

Gate Level Modelling Using Verilog:

  • Procedure for Installation and Simulation of Modelsim. Basic Verilog syntax. Dataflow flow style of modelling with Hands on examples
  • Structural  style of modelling with Hands on examples
  • Behavioural  style of modelling with Hands on examples
  • FPGA and ASIC Based Synthesis- Test Bench Writing
  • FSM Design- Mealy or Moore machines

 

Tools:

Front End Analog Tool    : 1) Modelsim (Free student versions)- For Gate level Design

 

Target Audience:

The workshop can be attended by Research scholars, Faculty members, U.G/ P.G students from ECE/EEE/TCE, and Industry Professionals.

 

Resource Person:

Dr. R. Sakthivel Ramachandran M.E, Ph.D.,

Sr. IEEE ACM’s Distinguished Speaker,

VIT Vellore.

 

Schedule:

Date : 17.6.2021 to 19.6.2021

Timing: 5.30 PM to 7.00 PM

 

Take Aways:

  • A Complete Practical Knowledge on VLSI System Design
  • Workshop Certification
  • Materials
  • Recorded Videos
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