Online Store - 8925533488 /89
Chennai - 8925533480 /81
Hyderabad - 8925533482 /83
Vijayawada -8925533484 /85
Covai - 8925533486 /87
2021-06-17 17:30 to 2021-06-19 19:00
June 17, 2021
https://www.pantechelearning.com/Organizer's other events
This workshop provides participants an insight into the processes involved in taking a Analog and Digital System Design. Whilst emphasizing the online tools’ availability and their installation procedures, this workshop also focuses on simulating several other experiments below, to develop the basic understanding of the VLSI System design using HDL.
Gate Level Modelling Using Verilog:
Front End Analog Tool : 1) Modelsim (Free student versions)- For Gate level Design
The workshop can be attended by Research scholars, Faculty members, U.G/ P.G students from ECE/EEE/TCE, and Industry Professionals.
Dr. R. Sakthivel Ramachandran M.E, Ph.D.,
Sr. IEEE ACM’s Distinguished Speaker,
Date : 17.6.2021 to 19.6.2021
Timing: 5.30 PM to 7.00 PM