Course on High Speed CMOS Logic Design using LTSpice
LESSON 1:
- – MOS Capacitors
- – Method of Logical Effort
- – Transistor Sizing for Minimum Delay
- – Path Sizing for Minimum Delay
- – Stick Diagram
- – Area Estimation
Course on High Speed CMOS Logic Design using LTSpice
LESSON 2:
- – Schematic Based Design Entry
- – Pre-Layout Simulation
- – Measurement of FoMs
- – Corner Analysis
- – Monte Carlo Simulation
LESSON 3:
- – Layout of CMOS Circuit
- – DRC Check
- – LVS Check
- – Post Layout Simulation
- – Measurement of FoMs
- – Comparison of Pre-Layout and Post Layout Simulation
Tools:
- Open-source Tools (LTSpice and ELECTRIC)
Resource Person:
Dr. Naushad Alam,
Ph.D. from IIT Roorkee,
Department of Electronics Engineering,
ZHCET, AMU Aligarh University.
Take-Aways:
- A Complete Practical Knowledge on CMOS Design
- Workshop Certification
- Materials
- Recorded Videos
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