This course provides participants an insight into the processes involved in taking an Analog and Digital System Design. Whilst emphasizing the online tools’ availability and their installation procedures, this workshop also focuses on simulating several other experiments below, to develop the basic understanding of the VLSI System design using HDL.
Gate Level Modelling Using Verilog:
- Procedure for Installation and Simulation of Modelsim. Basic Verilog syntax. Dataflow flow style of modeling with Hands-on examples
- Structural style of modeling with Hands-on examples
- Behavioral style of modeling with Hands-on examples
- FPGA and ASIC Based Synthesis- Test Bench Writing
- FSM Design- Mealy or Moore machines
Tools:
Front End Analog Tool: 1) Modelsim (Free student versions)- For Gate level Design
Take-Aways:
- A Complete Practical Knowledge on VLSI System Design
- Course Certification
- Materials
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