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Showing 43–60 of 60 results
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Design of Low Power High Speed Fully Dynamic CMOS Latched Comparator
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Design of Low Power High Speed Fully Dynamic CMOS Latched Comparator
SKU:
PAN_VLSI_048
Category:
VLSI Projects
High Performance Wallace Multiplier using Modified Full Adder in Reversible Logic Structure
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High Performance Wallace Multiplier using Modified Full Adder in Reversible Logic Structure
SKU:
PAN_VLSI_049
Category:
VLSI Projects
A Novel high speed dynamic comparator with low power dissipation
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A Novel high speed dynamic comparator with low power dissipation
SKU:
PAN_VLSI_050
Category:
VLSI Projects
Design of 4:2 Compressor based Approximate Booth multiplier
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Design of 4:2 Compressor based Approximate Booth multiplier
SKU:
PAN_VLSI_051
Category:
VLSI Projects
Design of Linear Feedback Shift Register for Test Pattern Generator
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Design of Linear Feedback Shift Register for Test Pattern Generator
SKU:
PAN_VLSI_052
Category:
VLSI Projects
Design of Optimized proposed 9T SRAM Cell
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Design of Optimized proposed 9T SRAM Cell
SKU:
PAN_VLSI_053
Category:
VLSI Projects
Design and Implementation of 4-2 Compressor design with new Xor-Xnor
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Design and Implementation of 4-2 Compressor design with new Xor-Xnor
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PAN_VLSI_054
Category:
VLSI Projects
Low power High Speed Adversarial Attack based 4:2 compressor as Full Adder for Multipliers
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Low power High Speed Adversarial Attack based 4:2 compressor as Full Adder for Multipliers
SKU:
PAN_VLSI_055
Category:
VLSI Projects
Majority logic based approximate adders and multipliers for error tolerant applications
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Majority logic based approximate adders and multipliers for error tolerant applications
SKU:
PAN_VLSI_056
Category:
VLSI Projects
4 bit Array Multiplier with Attacked 4:2 compressor(Full Adder)
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4 bit Array Multiplier with Attacked 4:2 compressor(Full Adder)
SKU:
PAN_VLSI_057
Category:
VLSI Projects
Implementation of Reed-Solomon Encoder for Wireless Network 802.16
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Implementation of Reed-Solomon Encoder for Wireless Network 802.16
SKU:
PAN_VLSI_030
Category:
VLSI Projects
32-bit ALU Design using Vedic Mathematics
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32-bit ALU Design using Vedic Mathematics
SKU:
PAN_VLSI_031
Category:
VLSI Projects
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
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Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
SKU:
PAN_VLSI_060
Category:
VLSI Projects
A Fully Static Topologically-Compressed 21-TransistorFlip-Flop
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A Fully Static Topologically-Compressed 21-TransistorFlip-Flop
SKU:
PAN_VLSI_033
Category:
VLSI Projects
Design and implementation of Median Architecture for Image Filtering Applications
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Design and implementation of Median Architecture for Image Filtering Applications
SKU:
PAN_VLSI_062
Category:
VLSI Projects
High Performance Array Multiplier using Reversible Logic Structure
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High Performance Array Multiplier using Reversible Logic Structure
SKU:
PAN_VLSI_058
Category:
VLSI Projects
Design of Low Power Adder and Multiplier Using Reversible Logic Gates
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Design of Low Power Adder and Multiplier Using Reversible Logic Gates
SKU:
PAN_VLSI_059
Category:
VLSI Projects
Design of Low Power and High Speed Dynamic Latch Comparator using 180 nm Technology
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Design of Low Power and High Speed Dynamic Latch Comparator using 180 nm Technology
SKU:
PAN_VLSI_061
Category:
VLSI Projects
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